class AVR8
{
public:
    typedef volatile unsigned char  Reg8;
    typedef volatile unsigned short Reg16;
    typedef volatile unsigned char  IOReg8;

    Reg8 r0; 
    Reg8 r1; 
    Reg8 r2; 
    Reg8 r3; 
    Reg8 r4; 
    Reg8 r5; 
    Reg8 r6; 
    Reg8 r7; 
    Reg8 r8; 
    Reg8 r9; 
    Reg8 r10; 
    Reg8 r11; 
    Reg8 r12; 
    Reg8 r13; 
    Reg8 r14; 
    Reg8 r15; 
    Reg8 r16; 
    Reg8 r17; 
    Reg8 r18; 
    Reg8 r19; 
    Reg8 r20; 
    Reg8 r21; 
    Reg8 r22; 
    Reg8 r23; 
    Reg8 r24; 
    Reg8 r25; 
    union {
	struct{Reg8 r26; Reg8 r27;};
	Reg16 x;
    };
    union {
	struct{Reg8 r28; Reg8 r29;};
	Reg16 y;
    };
    union {
	struct{Reg8 r30; Reg8 r31;};
	Reg16 z;
    };
};

class AT90S: public AVR8
{
public:
    static const unsigned short RAM_SIZE   = 0x0200;

public:
    IOReg8 reserved_00;	// [0x20]
    IOReg8 reserved_01;	// [0x21]
    IOReg8 reserved_02;	// [0x22]
    IOReg8 reserved_03;	// [0x23]
    IOReg8 reserved_04;	// [0x24]
    IOReg8 reserved_05;	// [0x25]
    IOReg8 reserved_06;	// [0x26]
    IOReg8 reserved_07;	// [0x27]
    IOReg8 acsr;	// [0x28]   
    IOReg8 ubrr;	// [0x29]
    IOReg8 ucr;		// [0x2A]
    IOReg8 usr;		// [0x2B]
    IOReg8 udr;		// [0x2C]
    IOReg8 spcr;	// [0x2D]
    IOReg8 spsr;	// [0x2E]
    IOReg8 spdr;	// [0x2F]
    IOReg8 ind;		// [0x30]
    IOReg8 ddrd;	// [0x31]
    IOReg8 portd;	// [0x32]
    IOReg8 inc;		// [0x33]
    IOReg8 ddrc;	// [0x34]
    IOReg8 portc;	// [0x35]
    IOReg8 inb;		// [0x36]
    IOReg8 ddrb;        // [0x37]
    IOReg8 portb;       // [0x38]
    IOReg8 ina;		// [0x39] 
    IOReg8 ddra;	// [0x3A] I/O port A direction (1->out, 0->in)
    IOReg8 porta;	// [0x3B] I/O port A data
    IOReg8 eecr;	// [0x3C] 
    IOReg8 eedr;	// [0x3D]
    IOReg8 eearl;	// [0x3E]
    IOReg8 eearh;	// [0x3F]
    IOReg8 reserved_20; // [0x40]
    IOReg8 wstcr;	// [0x41]
    IOReg8 reserved_22;	// [0x42]
    IOReg8 reserved_23;	// [0x43]
    IOReg8 icr1l;	// [0x44]
    IOReg8 icr1h;	// [0x45]
    IOReg8 reserved_26;	// [0x46]
    IOReg8 reserved_27;	// [0x47]
    IOReg8 ocr1bl;	// [0x48]
    IOReg8 ocr1bh;	// [0x49]
    IOReg8 ocr1al;	// [0x4A]
    IOReg8 ocr1ah;	// [0x4B]
    IOReg8 tcnt1l;	// [0x4C]
    IOReg8 tcnt1h;      // [0x4D]
    IOReg8 tccr1b;	// [0x4E]
    IOReg8 tccr1a;	// [0x4F]
    IOReg8 reserved_30;	// [0x50]
    IOReg8 reserved_31;	// [0x51]
    IOReg8 tcnt0;	// [0x52]
    IOReg8 tccr0;	// [0x53]
    IOReg8 reserved_34;	// [0x54]
    IOReg8 mcucr;	// [0x55]
    IOReg8 reserved_36;	// [0x56]
    IOReg8 reserved_37;	// [0x57]
    IOReg8 tifr;	// [0x58]
    IOReg8 timsk;	// [0x59]
    IOReg8 gifr;	// [0x5A]
    IOReg8 gimsk;	// [0x5B]
    IOReg8 reserved_3c;	// [0x5C]
    IOReg8 spl;		// [0x5D]
    IOReg8 sph;		// [0x5E]
    IOReg8 sreg;	// [0x5F]

    char ram[RAM_SIZE];
};


class Wrapper {
	
	protected:
		AT90S * at90s;
	public:	
		Wrapper(){
			at90s = reinterpret_cast<AT90S *>(0);
			at90s->ddrb   = 0xff; // Set PORTB to output
			at90s->portb  = 0xff; // Turn off LEDs
			at90s->sreg   = 0x80; // Enable Interrupts
			at90s->gimsk  = 0x40; // Enable External Interrupt 0
			at90s->timsk |= 0x80; // Enable Timer1 Overflow Interrupt
			at90s->mcucr  = 0x02;// Interrupt 0 generated by falling edge
		}

		~Wrapper(){}

		void handle_int0() {
			if(at90s->mcucr == 0x03) {    // If IRQ0 is rising edge (button released)
				at90s->mcucr  = 0x02; // Set IRQ0 to falling edge
				at90s->portb  = 0xff;
				at90s->tccr1b = 0x00; // Disable TIMER1 
			} else {		      // IRQ1 is falling edge (button pressed)
				at90s->mcucr  = 0x03;
				at90s->tccr1b = 0x04; // Start TIMER1 @ CLK/256
			}
		}

		void handle_timer1() {
			at90s->portb = 0xaa;
		}
};


Wrapper wrapper;

extern "C" {
	void __vector_1() __attribute__ ((signal));/* IRQ 0 Interrupt Handler */
	void __vector_7() __attribute__ ((signal));/* Timer1 Interrupt Handler */
}

void __vector_1(){
	wrapper.handle_int0();
}

void __vector_7(){
	wrapper.handle_timer1();
}

int main() {
    while(1) 
    return 0;
}