The purpose of this exercice is to get you acquitted with the
process of integrating, compiling and synthetising microcontroller
IP components. The task is to build a simple calculator for
the Pegasus/Picoblaze platform.
The hardware/software platform for this exercice is comprised by
several different items:
- The Pegasus Spartan-II Board:
board from Digilent Inc. has a built-in
Spartan-II FPGA from Xilinx, a configuration ROM, and several
peripherals (8 switches, 4 pushbuttons, 4 SSDs and 8 LEDs).
You'll probably want to take a look at the
- The Picoblaze IP Component
This VHDL component contains the implementation for the Picoblaze
soft-processor. The Picoblaze appnote
contains information regarding implementation, usage and
functionality (registers, instruction set, etc).
- The Pegasus/Picoblaze system
This is an implementation of a Picoblaze
microcontroller environment for the Pegasus board. It is comprised
by several elements:
- kcpsm.vhd and embedded_kcpsm.vhd
These are the files that define the Picoblaze processor and connect
it to the program ROM memory.
This is the program memory definition file. It is generated by
the Picoblaze assembler.
This component performs automatic conversion of hexadecimal values
to SSD codes.
This is the top component for this implementation, and connects
the Picoblaze to the Pegasus board's peripherals.
This is a constraints file that specifies the actuals pins connecting
the FPGA to the Pegasus peripherals in this system.
- The Picoblaze Assembler
Xilinx ISE Platform
In this development flow, you need to generate hardware as well as
software. Each time you build a new application and assemble it
with the Picoblaze assember, you will have a new .vhd file that
contains the memory definitions for your application. With this new
definition, you will run through the synthesis process through ISE
Project Manager, and implement it in the Pegasus Board by downloading
the new bitfile into the FPGA with ISE Impact
For this exercice, you will implement a simple calculator for
the Picoblaze/Pegasus system, for which the following functionalities
- Operand inputs are determined by hexadecimal value presented by
the switches. The current switches value is presented in the SSDs,
except when a result is requested. An operand is read when an
operation is selected.
- A sum (+) operation is selected by button 0. When a sum operation
is selected, the current switches value is read and added to the
- A subtraction (-) operation is selected by button 1. When a
subtraction operation is selected, the current switches value
is read and subtracted from the current result.
- Button 2 resets the result register.
- While Button 3 is pressed, the current result is presented in
- LED 0 signalizes a negative result.
- LED 7 signalizes overflow.
In the first version, the result register is 8-bit wide. In the
final version, it must be 16-bit wide.