Implementation of priority queue


The goal of this exercise is to implement a RTL priority queue using a hardware description language and then deploy the design in a FPGA platform.

User interface

Consider the development kit of the previous exercise:


The queue must have the following interface:

It is up to the students to define the implementation methodology as well as the HDL they are going to use. The design must only met the following requirements:

Check the previous exercise for useful resources.